The present disclosure relates to processor systems, and more specifically, to a system and method for invalidating an effective address to real address translation in a processor capable of performing multiple parallel memory accesses.
Consistent with the drive to improve processor performance, computer architects may incorporate processor subsystems having multiple parallel execution units into the design of central processing units (CPU). The term “execution units” refer generally to hardware units inside a processor, separate from the CPU cores that may be optimized to perform a dedicated set of calculations and operations on the behalf of a thread or process. Execution units may include data accelerators, memory management units, and dynamic memory access (DMA) controllers. The execution units improve the overall performance of a computing system by offloading from the CPU computationally intensive, yet commonly executed tasks, such as data compression, encryption, and signal processing. In the course of carrying out these tasks, execution units may issue memory access requests for loading source data for processing, or storing target (or output) data. The CPU's performance may be optimized by ensuring that a constant stream of data is fed to, and retrieved from, the execution units. This goal may be achieved by incorporating multiple parallel memory access entities (MAEs) in processor subsystems having execution units. An execution unit such as a DMA controller may use the MAEs to help mask memory access and bus latencies by prefetching source data and performing buffered writes of target data for multiple execution units in parallel.